Within a state-of-the-art processor, a function is often provided which enables the processor to count the occurrences of performance events in the data processing system and to time the execution of processes within the data processing system, etc. Such a function is known as the performance monitoring of the processor, and is implemented by a performance monitoring system in the processor.
In a data processing system comprising such a processor, most of occurring performance events can be counted by one or more counters in the performance monitoring system of the processor. Such a counter comprises a plurality of bit fields, and its operation is managed by a control register in the processor. Generally, such a control register and counters both can be read and written by software in the data processing system. Therefore, by using the software to write a corresponding value into the control register, the user can select the type of performance events to be monitored in the data processing system and specify the activation conditions for the counter for counting this type of performance events.
In the U.S. Pat. No. 5,555,748, entitled “Method and system for performance monitoring within a data processing system”, is disclosed a performance monitoring system, an schematic structure of which is shown in FIG. 1. As shown, the performance monitoring system comprises a multiplexer 14 and a performance event incrementer 10. The multiplexer 14 is configured to receive on lines 16 a plurality of performance event signals from various locations in the circuitry to be monitored in the data processing system. In addition, a mode_select signal on a line 15 is configured to determine which performance event signals in the plurality of performance event signals may be transmitted through the multiplexer 14 to the performance event incrementer 10. The performance event incrementer 10 is configured to, under being triggered by the selected performance event signals, count the occurrences of the performance events to which the performance event signals correspond. That is, the performance event signal is transmitted through the multiplexer 14 on a control line 20, so that the performance event incrementer 10 can count the occurrences of the performance events to which the performance event signals correspond.
In particular, in the performance event incrementer 10, a multiplexer 12 receives as inputs the value of a register 11 on a line 18 and the value incremented by an incrementer logic 13 on a line 17. Thus, when the selected performance event signal on the line 20 is high (logical “one”), the multiplexer 12 transmits the signal on the line 17 to the register 11. At this point, the input on the line 17 is equal to the value of the output of the register 11 incremented by 1 through the incrementer logic 13. Therefore, the final output of the register 11 on a line 19 represents the final counting value of the performance incrementer 10. This value is equal to the total occurrences of the performance events monitored in the data processing system.
In summary, in the performance monitoring system as shown in FIG. 1, for a specified time slice, only performance event count incrementing is triggered by the monitored performance event signals, thus only statistical data of the performance events is provided for use by a performance analysis tool in the data processing system in analyzing the behavior of the system. However, in scenarios where the performance analysis tool performs performance analysis and debugging for a multithread application, for example, the timestamp of each time-related performance event is also a very important information. Thus, in order to track a specific performance event within a specific time slice, not only the performance events themselves, but also the timestamps of the performance events should be recorded for use by the performance analysis tool in event analysis. Further, for most data processing systems, there are generally multiple thousands of events occurring within a time period intended for event analysis, and if the performance monitoring system as shown in FIG. 1 is employed, sufficient event counters would be needed to track all the events, which is apparently not feasible.
In addition, in the U.S. Pat. No. 6,775,640, entitled “Performance adder for tracking occurrence of events within a circuit”, is disclosed a performance monitoring system, comprising a signal detection logic circuit for tracking various types of performance event signals in the circuitry to be monitored. FIG. 2 shows a schematic structure of such a signal detection logic circuit. As shown, the signal detection logic circuit 50 comprises event type logic blocks: an atomic logic block 45, an edge logic block 46 and a toggle or on/off logic block 47. For example, a signal 0 on a line 51 is transmitted to the atomic logic 45 for atomic signal detection, to the edge logic block 46 for edge signal detection, and to the toggle or on/off logic block 47 for toggle or on/off signal detection. Then the performance event signals generated by each of the atomic logic, edge logic and toggle or on/off logic are transmitted to the multiplexer 43. The multiplexer 43 is controlled by a type_select signal on a line 44 for selecting the type (atomic, edge or toggle) of the performance event signal to be transmitted to a multiplexer 37, which then can selectively transmit the selected performance event signal to a performance event incrementer 10 in a next stage which is not shown.
If a signal detection logic circuit as shown in FIG. 2 is employed, for each signal line in the circuitry to be monitored, such a specific signal detection logic and a type selection register for controlling the multiplexer would need to be provided. However, among these signal detection logic circuits, only the signal detection logic circuit for the signal line selected by the multiplexer 37 is in operation at a time, thus causing a tremendous waste of resources. Further, the signal detection logic circuit further cannot track multiple bit signals associated, such as those representing the status of the processor, so that the detection of a performance event generated by a combination of multiple bit signals can not be realized.